X-Git-Url: https://osm.etsi.org/gitweb/?a=blobdiff_plain;f=httpserver.py;h=9f2673711bb756958b702751a72afce867bc3449;hb=refs%2Fchanges%2F07%2F707%2F1;hp=870d680247f4f4b398c5a80a2881c86c75ab946f;hpb=6560f21916b311a7fa63fffaf7e74bd212b9d25c;p=osm%2Fopenvim.git

diff --git a/httpserver.py b/httpserver.py
index 870d680..9f26737 100644
--- a/httpserver.py
+++ b/httpserver.py
@@ -599,7 +599,6 @@ def http_post_hosts():
                                 sriov['source_name'] = index
                                 index += 1
                             interfaces.append  ({'pci':str(port_k), 'Mbps': port_v['speed']/1000000, 'sriovs': new_sriovs, 'mac':port_v['mac'], 'source_name':port_v['source_name']})
-            #@TODO LA memoria devuelta por el RAD es incorrecta, almenos para IVY1, NFV100
             memory=node['memory']['node_size'] / (1024*1024*1024)
             #memory=get_next_2pow(node['memory']['hugepage_nr'])
             host['numas'].append( {'numa_socket': node['id'], 'hugepages': node['memory']['hugepage_nr'], 'memory':memory, 'interfaces': interfaces, 'cores': cores } )